`timescale 1 ns/ 1 ns
module riscv_vlg_tst();

// time_clk
reg clk = 1'b0;
always clk = #20 ~clk;

//restart
reg rst = 1'b1;
initial #40 rst = 1'b0;

wire uart_out;

//sram begin
/*reg [7:0] sram [8192];

integer fd,fx;
initial begin
	$readmemh ("../testfiles/test.data", sram);
end 

wire [31:0] sram_addr;
reg [31:0] sram_data;
reg [31:0] sram_data2;
wire [31:0] sram_data1;
wire [31:0] sram_addr1;
wire sram_en;
wire sram_rw;//0read,1write
wire [3:0] sram_byte_enable;

always @ ( * )
	sram_data <= {sram[sram_addr+3],sram[sram_addr+2],sram[sram_addr+1],sram[sram_addr]};
always @ ( * )
	sram_data2 <= {sram[sram_addr1+3],sram[sram_addr1+2],sram[sram_addr1+1],sram[sram_addr1]};
	
assign	sram_data1 = (sram_en == 1 && sram_rw == 0)?sram_data2:{32{1'bz}};

reg tx_vld_cout = 0;
always @ ( * ) begin
	if(sram_en && sram_rw == 1 && sram_byte_enable[3])
		sram[sram_addr1+3] <= sram_data1[31:24];
	if(sram_en && sram_rw == 1 && sram_byte_enable[2])
		sram[sram_addr1+2] <= sram_data1[23:16];
	if(sram_en && sram_rw == 1 && sram_byte_enable[1])
		sram[sram_addr1+1] <= sram_data1[15:8];
	if(sram_en && sram_rw == 1 && sram_byte_enable[0])
		sram[sram_addr1] <= sram_data1[7:0];
end		

always @ ( posedge clk) begin
	if(sram_en && sram_addr1 == 32'h1ff4 && sram_rw)
		$write("%c", sram_data1[7:0]);
	if(sram_en && sram_addr1 == 32'h1ff3 && sram_rw)
		$write("%c", sram_data1[15:8]);
	if(sram_en && sram_addr1 == 32'h1ff2 && sram_rw)
		$write("%c", sram_data1[23:16]);
	if(sram_en && sram_addr1 == 32'h1ff1 && sram_rw)
		$write("%c", sram_data1[31:24]);
end*/
//sram end

//unit begin
riscv_min_sopc u_riscv(
	.clk_i(clk),
	.rst(rst),
	
	.uart_out(uart_out)
);
//unit end

//test begin
initial                                                
begin                                                                                         
	$display("Running testbench");   
	#2000000 $finish;
end    
//read
always @(posedge clk) begin  
	// $display ("Now : addr: %8h data:%8h.",sram_addr-4 ,sram_data);
	// $display ("Ref : %8h.",{sram[sram_addr-1],sram[sram_addr-2],sram[sram_addr-3],sram[sram_addr-4]});
end    
//test end

//wave output
initial begin
	//$dumpfile("./dump.vcd");
	$dumpvars;
end
                                                
endmodule

